.include	"2313def.inc"
.include	"video.inc"
.cseg
	rjmp	RESET

SEGDATA:
	.db		0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x27,0x7f,0x67
RESET:
	outi	SPL,RAMEND		;SPの初期化
	ldi		R22,0xfe		;for PORTB
	ldi		R23,1			;for PB0 reverse
	out		PORTB,R23		;rrrrrrr0	...PB1〜7をプルアップ
	outi	DDRB,0x01		;iiiiiiio	...PORTBの入出力設定
	outi	PORTD,0x53		;xr0100rr	...0 IRE(4<<2), PD0をプルアップ
	outi	DDRD,0x3c		;xxooooxi	...PORTDの入出力設定
;************************************************************

START:
	ldi		R20,9
NUMLOOP:
	sbis	PIND,0			;(+2)
	rjmp	START
	lpmtab	SEGDATA,R20
	rcall	numdisp
	djnz	R20,NUMLOOP

LOOP:
	sbis	PIND,0			;(+2)
	rjmp	START

	rcall	csync
	ldi		R17,181
FLOOP1:						;21〜201
	rcall	hblank
	rcall	video1
	djnz	R17,FLOOP1
	ldi		R17,61
FLOOP2:						;202〜262
	rcall	hblank
	rcall	video2
	djnz	R17,FLOOP2
	rjmp	LOOP

numdisp:
	ldi		R18,60
number:
	sbis	PORTD,0			;(+2)
	rjmp	START
	pb0rev
	rcall	csync
	pb0rev
	ldi		R17,34
	rcall	blackline		;21〜60
	pb0rev
	rcall	seg_a			;61〜80
	pb0rev
	rcall	seg_fb			;81〜128
	pb0rev
	rcall	seg_g			;129〜148
	pb0rev
	rcall	seg_ec			;149〜196
	pb0rev
	rcall	seg_d			;197〜216
	pb0rev
	ldi		r17,46
	rcall	blackline		;217〜262
	djnz	R18,number
	ret
;************************************************************
blackline0:
	rjmp	PC+1			;***
	rjmp	PC+1			;***
	rjmp	PC+1			;***
	rjmp	PC+1
	rjmp	PC+1
	rjmp	PC+1
blackline:
	rcall	hblank
	irelen	IRE0,188
	djnz	R17,blackline0	;2/1
	ret						;4

seg_a0:
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1
	rjmp	PC+1
	rjmp	seg_a1
seg_a:
	ldi		R17,20
seg_a1:						;61〜80
	rcall	hblank
	irelen	IRE0,118
	sbrs	R0,0			;bit test a
	rjmp	seg_a2
	irelen	IRE100,39		;a1 on
	rjmp	seg_a3
seg_a2:
	irelen	IRE0,39			;a1 off
	nop
seg_a3:
	irelen	IRE0,30
	djnz	R17,seg_a0
	ret

seg_fb0:
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1
	rjmp	PC+1
	rjmp	seg_fb1
seg_fb:
	ldi		R17,48
seg_fb1:					;81〜128
	rcall	hblank
	irelen	IRE0,108
	sbrs	R0,5			;bit test f
	rjmp	seg_fb2
	irelen	IRE100,9		;f1 on
	rjmp	seg_fb3
seg_fb2:
	irelen	IRE0,9			;f1 off
	nop
seg_fb3:
	irelen	IRE0,40
	sbrs	R0,1			;bit test b
	rjmp	seg_fb4
	irelen	IRE100,9		;b1 on
	rjmp	seg_fb5
seg_fb4:
	irelen	IRE0,9			;b1 off
	nop
seg_fb5:
	irelen	IRE0,20
	djnz	R17,seg_fb0
	ret

seg_g0:
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1
	rjmp	PC+1
	rjmp	seg_g1
seg_g:
	ldi		R17,20
seg_g1:						;61〜80
	rcall	hblank
	irelen	IRE0,118
	sbrs	R0,6			;bet test g
	rjmp	seg_g2
	irelen	IRE100,39		;g1 on
	rjmp	seg_g3
seg_g2:
	irelen	IRE0,39			;g1 off
	nop
seg_g3:
	irelen	IRE0,30
	djnz	R17,seg_g0
	ret

seg_ec0:
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1
	rjmp	PC+1
	rjmp	seg_ec1
seg_ec:
	ldi		R17,48
seg_ec1:					;81〜128
	rcall	hblank
	irelen	IRE0,108
	sbrs	R0,4			;bit test e
	rjmp	seg_ec2
	irelen	IRE100,9		;e1 on
	rjmp	seg_ec3
seg_ec2:
	irelen	IRE0,9			;e1 off
	nop
seg_ec3:
	irelen	IRE0,40
	sbrs	R0,2			;bit test c
	rjmp	seg_ec4
	irelen	IRE100,9		;c1 on
	rjmp	seg_ec5
seg_ec4:
	irelen	IRE0,9			;c1 off
	nop
seg_ec5:
	irelen	IRE0,20
	djnz	R17,seg_ec0
	ret

seg_d0:
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1	;***
	rjmp	PC+1
	rjmp	PC+1
	rjmp	seg_d1
seg_d:
	ldi		R17,20
seg_d1:						;129〜148
	rcall	hblank
	irelen	IRE0,118
	sbrs	R0,3			;bit test d
	rjmp	seg_d2
	irelen	IRE100,39		;d1 on
	rjmp	seg_d3
seg_d2:
	irelen	IRE0,39			;d1 off
	nop
seg_d3:
	irelen	IRE0,30
	djnz	R17,seg_d0
	ret

video1:						;video: 188
	irelen	IRE100,31		;WHITE
	sc30	IRE100,IRE10	;CYAN
	nop						;sc shift 90deg
	sc30	IRE90,IRE10		;GREEN
	nop						;sc shift 90deg
	sc30	IRE70,IRE_10	;RED
	nop						;sc shift 90deg
	sc30	IRE40,IRE_10	;BLUE
	irelen	IRE0,36			;BLACK
	ret

video2:						;video: 188
	irelen	IRE80,40		;GRAY
	irelen	IRE60,40		;GRAY
	irelen	IRE40,40		;GRAY
	irelen	IRE10,68		;GRAY
	ret

;************************************************************
csync:
	rcall	eqpulse			;1
	rcall	eqpulse			;2
	rcall	eqpulse			;3
	rcall	vsync			;4
	rcall	vsync			;5
	rcall	vsync			;6
	rcall	eqpulse			;7
	rcall	eqpulse			;8
	rcall	eqpulse			;9
	ldi		R17,11
HSLOOP:
	rcall	hblank			;10〜20
	irelen	IRE0,188
	djnz	R17,HSLOOP
	ret

eqpulse:
	irelen	IRE_40,8		;EQパルス
	irelen	IRE0,106
	irelen	IRE_40,8		;EQパルス
	irelen	IRE0,106
	ret

vsync:
	irelen	IRE_40,97		;VSYNCパルス
	irelen	IRE0,17
	irelen	IRE_40,97		;VSYNCパルス
	irelen	IRE0,17
	ret

hblank:
	irelen	IRE0,5			;フロントポーチ
	irelen	IRE_40,16		;HSYNC
	irelen2	IRE0
	sc8		IRE20,IRE_20
	irelen	IRE0,5
	ret

T_sc:						;(1+3)+1+4*(r16-3)-1+4...R16を3以上にしてcall
	subi	R16,3			;1
LOOP_sc:
	nop						;1
	dec		R16				;1
	brne	LOOP_sc			;1/2
	ret						;4